1. Field of the Invention
The present invention relates to a semiconductor memory and a fabrication method of the semiconductor memory. It is particularly related to a miniaturized nonvolatile semiconductor memory encompassing a plurality of memory cell transistors, each of the memory cell transistors being implemented by a gate electrode structure, which embraces an inter-electrode dielectric sandwiched between a first conductive layer and a second conductive layer. The semiconductor memory encompasses a plurality of cell columns, each of the cell columns embracing serially connected memory cell transistors, and the cell columns being arranged very close to each other.
2. Description of the Related Art
Semiconductor memory devices have been decreasing the inter-cell spacing at approximately 30% per annum through high integration and miniaturization. With nonvolatile semiconductor memories, it is possible to store information in a cell by retaining electric charges in a conductive layer (polycrystalline silicon) that maintains a floating state. With a miniaturized nonvolatile semiconductor memory, the opposing area of each first conductive layer (each floating gate electrode) and corresponding second conductive layer (corresponding control gate electrode) becomes smaller, however, it is necessary to ensure a sufficient capacitance between each first conductive layer and corresponding second conductive layer via corresponding inter-electrode dielectric. In other words, increasing the area in a three-dimensional structure becomes impossible as a result of the reduced inter-cell spacing, whereby it becomes necessary to use an insulating film with a higher dielectric constant than before as the inter-electrode dielectric. However, various inter-cell couplings have become problematic when a high dielectric material is applied as the inter-electrode dielectric.
For example, a nonvolatile semiconductor memory as shown in FIG. 1 has been proposed in relation to this inter-cell coupling (see Japanese Patent Application Laid-open No. 2001-168306). FIG. 1 is a schematic cross sectional view cut along the word line direction, where there are multiple memory cell regions isolated by device isolation films 7 on the surface of a semiconductor substrate (silicon substrate) 1. A gate insulator (tunnel insulator) 2, a first conductive layer (floating gate electrode) 3, inter-electrode dielectrics 9f, and a second conductive layer (control gate electrode) 10 are formed on the surface of the semiconductor substrate 1 in order in each memory cell region. In FIG. 1, the inter-electrode dielectrics 9f are separated between adjacent cells above the device isolation films 7. Then, the second conductive layer (control gate electrode) 10 is filled into the separating areas defined between adjacent inter-electrode dielectrics 9f. The T-shaped inter-electrode dielectric 9f, having projecting overhangs over the device isolation films 7, is provided on top surface of each first conductive layer (floating gate electrode) 3, and a couple of thin vertical walls (sheaths) comprised of a silicon oxide film 9g is arranged between the lower edges of the projecting overhangs implemented by each inter-electrode dielectric 9f and the top surface of the corresponding device isolation film 7.
The cell structure shown in FIG. 1 is an effective structure for prohibiting the transport of electric charges within the first conductive layers 3, preventing the movement of the electric charges between adjacent cells, interrupting the path between the adjacent inter-electrode dielectrics 9f. Furthermore, since the second conductive layer 10 is filled in between the adjacent wing-shaped (T-shaped) protruding portions of the first conductive layers 3, the capacitance between adjacent first conductive layers 3 does not increase. However, there are problems with the cell structure shown in FIG. 1 such that there is a risk of an occurrence of a short-circuit failure between the first and second conductive layers, and the manufacturing yield is reduced since electrical insulation between the first conductive layers 3 and the second conductive layer 10 depends on the weak insulation characteristic of the walls (sheaths) 9g implemented by the thin silicon oxide films.
FIG. 2 is a schematic cross sectional view cut along the word line direction of another earlier nonvolatile semiconductor memory. Differing from the structure shown in FIG. 1, an inter-electrode dielectric 9e is formed, covering the entire surface. Other features and the structure are the same as the features and structure of those shown in FIG. 1.
As shown in FIG. 2, a parallel-plate capacitance C1 is formed between the side surfaces of the adjacent first conductive layers 3, which are floating gate electrodes, and a bypassing edge-capacitance C2 is formed between the edges of the adjacent first conductive layers 3. The bypassing edge-capacitance C2 is ascribable to the edge electric field passing through the inter-electrode dielectric 9e. 
With miniaturized nonvolatile semiconductor memories, as the inter-cell spacing decreases, the so-called inter-cell coupling drastically increases between a ‘programmed cell’ retaining electric charges and an ‘erased cell’ not retaining electric charges. In the case of an example shown in FIG. 2, in which an insulating film with a higher relative dielectric constant ∈r than the device isolation film 7 for the inter-electrode dielectric 9e is employed, a bypassing edge-capacitance C2 via the inter-electrode dielectric 9e becomes greater than parallel-plate capacitance C1 between the first conductive layers 3, contributing to the problem of inter-cell coupling.
As it is known, electric displacement (dielectric flux density) vector D has a relationship with electric field vector E:D=∈0·∈r·E  (1)where ∈0 denotes the dielectric constant of vacuum, and ∈r denotes the relative dielectric constant. Accordingly, the dielectric flux within the dielectric material with relative dielectric constant ∈r is ∈0·∈r times the electric flux line. Eq. (1) means that, if relative dielectric constant ∈IP of the inter-electrode dielectric 9e is sufficiently higher than relative dielectric constant ∈STI of the device isolation films 7, electric displacement (dielectric flux density) vector D between adjacent first conductive layers (floating gate electrodes) 3 has a tendency to be confined in the inter-electrode dielectric 9e. 
Gauss's law in differential form:div D=ρ  (2)shows that the electric displacement vector D has a local relationship with electric charge density ρ. Then, dielectric fluxes of q lines originate from an electric charge q. On the other hand, capacitance C is represented by:C=q/V  (3)where V denotes inter-electrode potential difference. In other words, when relative dielectric constant ∈IP of the inter-electrode dielectric 9e is sufficiently higher than relative dielectric constant ∈STI of the device isolation films 7, more charges q are then induced on the upper corner of the mutually opposing first conductive layers 3 at the inter-electrode dielectric 9e side, and bypassing edge-capacitance C2 shown in FIG. 2 becomes relatively noticeable compared to parallel-plate capacitance C1.
Under a condition where parallel-plate approximation holds, with the film thickness of the first conductive layer (floating gate electrode) denoted as tFG, and the film thickness of the inter-electrode dielectric denoted as TIP, capacitance ratio C2/C1 of parallel-plate capacitance C1 to bypassing edge-capacitance C2 is generally represented by:C2/C1=(TIP·∈IP)/(tFG·∈STI)  (4)Eq. (4) is true in the case where the parallel-plate approximation holds, where the film thickness of the inter-electrode dielectric denoted as TIP is sufficiently small relative to the parallel-plate electrode area, and the electrode edge effect is negligible.
On the contrary, since the geometrical configuration implemented by the first conductive layers 3 and/or the inter-electrode dielectric 9e, as shown in FIG. 2, must consider a three-dimensional geometry effect, application of parallel-plate approximation is difficult. If the cross sectional view of FIG. 2 extends infinitely perpendicular to the plane of the paper so as to provide infinitely long first conductive layers 3, two-dimensional geometry effect must be considered, and application of the parallel-plate approximation is difficult. Although the exact solution must consider the three or two-dimensional geometry effect, when relative dielectric constant ∈IP of the inter-electrode dielectric 9e is sufficiently higher than relative dielectric constant ∈STI of the device isolation films 7, it is qualitatively understood that the bypassing edge-capacitance C2 ascribable to the electric field confined in the inter-electrode dielectric 9e may become noticeably large compared to the parallel-plate capacitance C1.
Thus, in the case of using a silicon oxide film (SiO2 film) with relative dielectric constant ∈r=3.8–4 as material for the device isolation films 7, usage of a high dielectric constant film, such as an alumina film (Al2O3 film) with relative dielectric constant ∈r=8–11, a hafnium oxide film (HfO2 film) with relative dielectric constant ∈r=22–23, a zirconium oxide film (ZrO2 film) with relative dielectric constant ∈r=22–23, or a tantalum oxide film (Ta2O5 film) with relative dielectric constant ∈r=25–27 causes a problem in which the bypassing edge-capacitance C2 becomes noticeable as a stray capacitance relative to the parallel-plate capacitance C1, resulting in an increase in the inter-cell coupling.